1. Technical Field of the Invention
The present invention relates to a sampling rate converter (SRC) that allows an increase or a decrease in the sampling rate.
2. Description of Related Art
Sampling rate converters are circuits which receive, as input, discrete values according to an input frequency, and which produce, as output, discrete values according to an output frequency, so that the values received and produced correspond respectively to reconstruction curves that are identical. The expression reconstruction curve of a sampled signal is understood to mean the analog signal continuous curve which is obtained by removing the spectral components of the sampled signal that appear at the harmonic frequencies of the sampling frequency. The conversion factor for the sampling rate is the quotient of the output frequency and the input frequency. When this factor is an integer greater than unity, the converter operates as an interpolator: it inserts additional values between the input values. When the conversion factor is an integer less than unity, the converter operates as a decimator: it removes certain of the input values. More generally, a conversion factor of greater than unity corresponds to an oversampling function, and a conversion factor of less than unity corresponds to an undersampling function.
Certain converters operate in digital mode: the input and output values are coded in bits. They may then incorporate, in a known manner, digital hardware such as adders and multipliers.
FIG. 1 is a schematic diagram of a first sampling rate converter of this type, known to the person skilled in the art, which allows an increase in the sampling rate. It comprises a chain of N identical cells connected in series, N being an integer greater than or equal to unity. The nth cell of this chain, denoted Cn, n being an integer lying between 1 and N, possesses a first input IN1(n), a second input IN2(n)) and a third input IN3(n) of respective digital values. It furthermore possesses a first output OUT1(n), a second output OUT2(n), and a third output (OUT3(n)) of digital values. For a cell Cn distinct from the last cell of the chain (n=1, . . . , N−1), the outputs OUT1(n) and OUT2(n) of this cell and its input IN3(n) are connected respectively to the inputs IN1(n+1) and IN2(n+1), and to the output OUT3(n+1) of the cell n+1, denoted Cn+1. The output OUT1(N) of the last cell of the chain, that is to say of the cell CN, is connected to the input IN2(N) of the same cell. The input IN1(1) of the cell C1 is intended to receive input sampling values IN, according to an input frequency fi. The input IN3(N) of the last cell of the chain receives a constantly zero value, denoted “0” in FIG. 1. The output OUT3(1) of the cell C1 delivers output sampling values OUT according to an output frequency f0.
Each cell comprises the following hardware:    two multipliers, referenced 13 and 17 for cell C1 in FIG. 1, N3 and N7 for cell CN;    a multiplicative coefficient storage element, referenced 10 for cell C1 and N0 for cell CN;    two adders, referenced 14 and 18 for cell C1, N4 and N8 for cell CN;    two flip-flops, referenced 12 and 16 for cell C1, N2 and N6 for cell CN. The flip-flops are denoted “Z−1” in FIG. 1; and    two multiplexers, referenced 11 and 15 for cell C1, N1 and N5 for cell CN.
The hardware items of each cell are connected together in the following manner, described for the cell C1, and corresponding to a so-called “direct” cell structure. First respective inputs of the multipliers 13 and 17 are connected to the storage element 10, and outputs of the multipliers 13 and 17 are connected respectively to first inputs of the two adders 14 and 18. The second input of the adder 14 constitutes the input IN3(1) of the cell C1, the output of the adder 14 is connected to the second input of the adder 18, and the output of the adder 18 constitutes the output OUT3(1) of the cell C1.
The second input of the multiplier 13 is linked to the input IN1(1) by the multiplexer 11 and the flip-flop 12. A first input of the multiplexer 11 constitutes the input IN1(1) of the cell C1, the output of the multiplexer 11 is connected to the input of the flip-flop 12, the output of the flip-flop 12 being connected to the second input of the multiplier 13 and to a second input of the multiplexer 11. The output of the flip-flop 12 furthermore constitutes the output OUT(1) of the cell C1.
The second input of the multiplier 17 is linked in an analogous manner to the input IN2(1) by the multiplexer 15 and the flip-flop 16, the output of the flip-flop 16 also constituting the output OUT2(1).
The multiplexers 11 and 15 furthermore receive on respective control inputs a signal Eni for controlling switching of the flip-flops 12 and 16. The signal Eni regulates the admission of new values IN into the flip-flops 12 and 16. The same control signal Eni is transmitted to the flip-flops of all the cells Cn of the chain corresponding to the flip-flops 12 or 16. It therefore regulates in a synchronized manner the propagation of the values IN throughout the chain. The signal Eni is adjusted in such a way that the output values OUT may be produced substantially at the frequency f0 in a manner compatible with a general gating clock (not represented in FIG. 1) of the converter.
The storage element 10 may be a permanent memory (ROM standing for Read Only Memory), or any other device for generating values, for example based on logic gates. The multiplicative coefficients recorded in the element 10 are, in a manner known to the person skilled in the art, certain values of the response characteristic of a low-pass type filter to an input pulse. Appropriate recording of the coefficients makes it possible to address, respectively to the multipliers 13 and 17, coefficients hi and hi* recorded in the element 10 at addresses that are complementary with respect to the entire set of addresses of the element 10. When the complete chain of cells C1, . . . , CN is implemented, an oversampling function is thus obtained between the input IN1(1) and the output OUT3(1), corresponding to a conversion factor of greater than unity.
FIG. 2 is a schematic diagram of a second sampling rate converter, also known to the person skilled in the art, which allows a decrease in the sampling rate. It also comprises a chain of N mutually identical cells, again referenced C1, . . . , CN. Each cell comprises the same hardware items as before, but connected differently. The structure of a cell of the converter of FIG. 2 is said to be “transverse,” in the jargon of the person skilled in the art.
With reference to the cell C1, and just as for the previous converter, the multipliers 13 and 17 receive, on first respective inputs, the multiplicative coefficients hi and hi* delivered by the storage element 10. They are each connected, by their second respective inputs, to the first input IN1(1) of the cell, and by their respective outputs to the first inputs of the adders 14 and 18.
A second input IN1′(1) of the cell C1 is linked to the second input of the adder 14 by a multiplexer 11′ and a flip-flop 12′. The input IN1′(1) is connected directly to the second input of the multiplexer 11′, and the output of the adder 14 is linked to the first input of the multiplexer 11′. The output of the multiplexer 11′ is connected to the input of the flip-flop 12′, and the output of the flip-flop 12′ is connected to the second input of the adder 14. The output of the adder 14 moreover constitutes a first output OUT1′(1) of the cell C1 of this converter.
The multiplexer 11′ is controlled by a signal En0. The signal En0 triggers the switchings of the flip-flop 12′ as well as the updates of the value delivered by the adder 14.
An identical link links a third input IN3(1) of the cell C1 to the second input of the adder 18. This link comprises the multiplexer 15′ and the flip-flop 16′. The second input of the multiplexer 15′ constitutes the input IN3(1), and the output of the adder 18 constitutes a second output OUT3(1) of the cell C1.
The successive cells of the chain are connected in the following manner: the input IN3(n) and the output OUT1′(n) of a cell n distinct from the last cell of the chain (n=1, . . . , N−1) are connected respectively to the output OUT3(n+1) and to the input IN1′(n+1) of the next cell Cn+1. The output OUT1′(N) of the last cell CN is connected to the input IN3(N) of this same cell. Furthermore, a zero value “0” is constantly applied to the input IN1′(1) of the cell C1.
All the cells receive, on their respective inputs IN1(1), . . . , IN1(N), the input values IN according to the frequency fi, and all the multiplexers 11′, . . . , N1′ and 15′, . . . , N5′ receive the control signal En0. When the complete chain of cells C1, . . . , CN is implemented, a subsampling function is obtained between the input IN1(1) and the output OUT3(1), corresponding to a conversion factor of less than unity. The signal En0 is adjusted so that the output values OUT are produced substantially according to the frequency f0, which is less than f1.
A drawback of the converters described above resides in the fact that each of them possesses either an oversampling function or an undersampling function. A complete sampling rate conversion function, whose conversion factor may be greater than or less than unity, can be obtained only by associating a first and a second converter respectively of the above types. However, such an embodiment requires double the number of certain of the hardware items such as the storage elements, the adders or the multipliers. Now, such hardware items are expensive.
There accordingly exists a need in the art for a single converter which can operate as an oversampler or as an undersampler.